The present invention relates generally to an apparatus and method for testing semiconductor devices. More particularly, the present invention relates to a test apparatus for packaged semiconductor devices that utilizes a pick-and-place mechanism to transfer the devices between and among various locations in the apparatus.
Integrated circuit (IC) devices are subjected to a variety of tests after fabrication. These tests occur before the IC is packaged and after the IC is packaged. The tests are designed to determine if the IC will meet performance and lifetime specifications.
Apparatus with many different configurations are used to test IC devices. In many apparatus, such as the apparatus described in U.S. Pat. No. 6,323,666 to Ohba et al., the IC's are loaded into some sort of test board for environmental testing. Typically, the apparatus performs some initial electrical tests on the IC before subjecting the device to the environmental testing. That way, the more expensive, time consuming environmental test is only performed on ICs that pass the initial test. Other apparatus that describe apparatus the perform some electrical testing of ICs prior to environmental testing are described in U.S. Pat. No. 4,902,969 to Gussman and U.S. Pat. No. 6,563,331 to Maeng.
Environmental testing is typically referred to as a burn-in test. The test is described as burn-in because it is done at an elevated temperature. Burn-in typically involves placing a large number of integrated circuit (IC) devices on printed circuit boards, referred to herein as test boards. The boards are placed in a chamber in which the environmental conditions, particularly temperature, are controlled. The IC devices are then subjected to electrical tests such as the application of DC current to forward and reverse bias the individual junctions in the IC or actively clocking the ICs to their maximum rated conditions. Running these tests at elevated temperature identifies ICs that do not perform according to their minimum specifications.
There are two major objectives associated with such testing. The first and foremost objective is to ensure that ICs that fail or are likely to fail are discovered and kept from being used (at least in the application for which they were identified as likely to fail). The failed ICs, once identified, might be recycled, repaired, retested, etc. The second equally important objective is that the good ICs are not falsely identified as bad ICs. Such misclassification has a number of downsides. First, it wastes an otherwise good IC by preventing it from being used for its intended purpose. Second, a series of false failures can give the impression of an artificially high fail rate. This could lead to an unnecessary, expensive, and time-consuming search for the source or sources of the fail rate.
Many apparatus have been proposed to more accurately identify failed ICs and to ensure that the ICs are not improperly identified as failures due to some defect or malfunction in the apparatus itself. One such approach is described in U.S. Pat. No. 6,323,666 to Ohba et al. With reference to FIG. 1, a test and burn-in system handler 10 is illustrated schematically. An electronic switch 4 is provided to switch between test signals of the IC test circuit 2 and the test signals of the burn-in board checker 3. The IC test circuit 2, the burn-in board checker 3 and the electrical switch 4 are made up as a unit.
The IC test circuit 2 is used to perform a pretest of the IC's 1A as the devices under test. The burn-in board checker 3 is for testing the burn-in board 1 to detect pattern disconnection, solder failure, short circuits or other defects. The alignment stage 6 is used to straighten the attitude of the IC's 1A.
The handler 10 is operated in the following manner. The carrier rack 8 has multiple burn-in boards 1, which, when loaded into the handler 10, do not contain IC devices. The burn-in boards 1, are inserted sequentially and each burn-in board, 1, is tested by the burn-in board checker 3 to determine if the burn-in board 1 contains any bad IC sockets. The burn-in board waits in this position to receive ICs 1A.
The ICs are transferred one at a time from the tray 5 to the alignment stage 6. After the attitudes of the ICs are straightened at the alignment stage 6, the ICs 1A are populated into the burn-in board 1. If the burn-in board has a defective socket, the loading software is instructed not to populate that socket with an IC.
After the burn-in board is loaded, the switch 4 is deployed to activate the IC test circuit 2. Simplified functional tests are performed on the ICs populating the burn-in board 1. After the electrical pretest, the ICs that are determined to be defective are removed from the burn-in board 1 while the devices that passed the pre-test remain. Once all of the normal sockets in the burn-in board 1 are loaded with ICs that were determined to be non-defective, the burn-in board is returned to the carrier rack 8. Once all of burn-in boards 1 in the carrier rack 8 are filled, the carrier rack is transferred to the burn-in apparatus.
While the apparatus described above achieves some efficiency and accuracy by testing individual sockets in burn-in boards before loading ICs therein, greater efficiency and flexibility for such test apparatus are sought while still ensuring the IC failures are properly attributed to the IC device, and not actually the result of a bad burn-in board socket or other extraneous reason.